Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets in registers and D-cache were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors is discussed.

[1]  E. A. Burke,et al.  Calculation of Cosmic-Ray Induced Soft Upsets and Scaling in VLSI Devices , 1982, IEEE Transactions on Nuclear Science.

[2]  L.W. Massengill,et al.  Single-event charge enhancement in SOI devices , 1990, IEEE Electron Device Letters.

[3]  Robert Ecoffet,et al.  Heavy ion test results on memories , 1992, Workshop Record 1992 IEEE Radiation Effects Data Workshop.

[4]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[5]  A. H. Johnston.  Radiation effects in advanced microelectronics technologies , 1997 .

[6]  S. F. Chu,et al.  SRAM bitline circuits on PD SOI: advantages and concerns , 1997 .

[7]  D. Schepis,et al.  Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies , 1997 .

[8]  M. Nakamura,et al.  A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[9]  N. Cohen,et al.  Soft error considerations for deep-submicron CMOS circuit applications , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[10]  Dimitri A. Antoniadis,et al.  Parasitic bipolar gain reduction and the optimization of 0.25-/spl mu/m partially depleted SOI MOSFETs , 1999 .

[11]  Hyungsoon Shin.  Modeling of alpha-particle-induced soft error rate in DRAM , 1999 .

[12]  S. Narasimha,et al.  A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[13]  M. Hussein,et al.  A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[14]  D. S. Walsh,et al.  SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments , 2001 .

[15]  Changhong Dai,et al.  Impact of CMOS process scaling and SOI on the soft error rates of logic processes , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

[16]  Farokh Irom,et al.  Single-event upset in the PowerPC750 microprocessor , 2001 .

[17]  Farokh Irom,et al.  Single-event upset in commercial silicon-on-insulator PowerPC microprocessors , 2002 .

[18]  Kevin Zhang,et al.  Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[19]  D. S. Walsh,et al.  Charge collection in SOI capacitors and circuits and its effect on SEU hardness , 2002 .

[20]  Claude Marcandella,et al.  Characterization of the parasitic bipolar amplification in SOI technologies submitted to transient irradiation , 2002 .

[21]  Philippe Roche,et al.  Comparison of the sensitivity to heavy ions of 0.25-/spl mu/m bulk and SOI technologies , 2002 .