In search of the optimum test set - adaptive test methods for maximum defect coverage and lowest test cost

Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec testing is still often necessary to ensure customer quality. Systematic defects are becoming more common and threaten to dominate the yield Pareto. Adaptive test methods are introduced in This work that demonstrate the capability of increasing or decreasing the test coverage based on the predicted or measured defect and parametric behavior of the silicon being tested. Results promise an increase in product quality at the same time a reduction in test costs.

[1]  David Turner,et al.  Screening minVDD outliers using feed-forward voltage testing , 2002, Proceedings. International Test Conference.

[2]  Wojciech Maly,et al.  Deformations of ic structure in test and yield learning , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[3]  Wen-Ben Jone,et al.  An adaptive path selection method for delay testing , 2001, IEEE Trans. Instrum. Meas..

[4]  Janusz Rajski,et al.  Affordable and effective screening of delay defects in ASICs using the inline resistance fault model , 2004 .

[5]  Claude Thibeault.  On new current signatures and adaptive test technique combination , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[6]  Shambhu J. Upadhyaya,et al.  Adaptive test scheduling in SoC's by dynamic partitioning , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[7]  Luigi Carro,et al.  A new adaptive analog test and diagnosis system , 2000, IEEE Trans. Instrum. Meas..

[8]  A. Cabbibo,et al.  Feed forward test methodology utilizing device identification , 2004 .

[9]  Edward J. McCluskey,et al.  Stuck-fault tests vs. actual defects , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Scott Benner,et al.  Optimal production test times through adaptive test programming , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  James McNames,et al.  Neighbor selection for variance reduction in I/sub DDQ/ and other parametric data , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[12]  W. Robert Daasch,et al.  Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[13]  W. Robert Daasch,et al.  Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[14]  Adit D. Singh,et al.  Burn-in failures and local region yield: an integrated field-reliability model , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[15]  Kenneth M. Butler,et al.  An empirical study on the effects of test type ordering on overall test efficiency , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).