Design and Analysis of Low Power Universal Line Encoder & Decoder

Communication plays an important role in day to day life. The information or data is transmitted through various techniques and line coding is one of the finest techniques for sending data. The selection of these techniques depends on the bandwidth requirement, DC level, bit error rate performance and the inbuilt error detection property. In this line coding techniques whose encoder and decoder have been designed and analyzed are Unipolar RZ, NRZ-I, NRZ-L, Manchester, Differential Manchester, AMI, Pseudoternary, B8ZS, HDB3 coding. Any one of these techniques can be access with the mode of selection. Switching activity is the one of the main factors that is responsible for the dynamic power dissipation. Power consumption by the encoders and decoders is directly proportional to switching activity. To optimize the power of the universal line encoder - decoder, Bus Shift (BS) coding scheme is applied that circularly shifts the data to minimize the transition. Simulation results show the average saving margin of power in universal encoder is 22% while in universal decoder saving margin is 35%. Keywords NRZ-I (Non Return To Zero Invert), NRZ-L (non return to zero level), AMI (alternate mark inversion), Manchester formats, pseudo ternary encoded format, B8ZS (bipolar eight zero substitution) and HDB3 (high density bipolar zero)

[1]  V. Veiko,et al.  Laser-Assisted Microtechnology , 1998 .

[2]  Rashid Rashidzadeh,et al.  Improved bus-shift coding for low-power I/O , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[3]  P G Scholar,et al.  VHDL IMPLEMENTATION OF MANCHESTER ENCODER AND DECODER , 2013 .

[4]  Wei Dang Implement of HDB3 coder in base-band system , 2012, 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet).

[5]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Yehea I. Ismail,et al.  Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[7]  Anjali.V P.Satishkumar Manchester Encoder and Decoder with Clock Recovery Unit and Invalid Detector , 2015 .

[8]  K. P. Sridhar,et al.  Test data compression using Hamming Encoder and Decoder for system on chip (SOC) testing , 2014, 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014].

[9]  M ShankaranarayanaBhat Universal Rotate Invert Bus Encoding for Low Power VLSI , 2012, VLSIC 2012.

[10]  Vivek Singh,et al.  FPGA IMPLEMENTATION OF VARIOUS LINES CODING TECHNIQUE FOR EFFICIENT TRANSMISSION OF DIGITAL DATA IN COMMUNICATION , 2014 .

[11]  Arun Khosla,et al.  Low Power Bus Encoding Techniques for Memory Testing , 2013 .

[12]  Prabhat Kumar Mishra,et al.  A Novel Approach for VHDL Implementation of Universal Line Encoder for Communication , 2010 .