A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm2. The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

[1]  Hoi-Jun Yoo,et al.  A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique , 2003 .

[2]  Albrecht Rothermel,et al.  Clock/data recovery PLL using half-frequency clock , 1997 .

[3]  Behzad Razavi.  A Versatile Clock Recovery Architecture and Monolithic Implementation , 1996 .

[4]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[5]  W.J. Dally,et al.  An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[6]  C. Hogge.  A self correcting clock recovery curcuit , 1985, Journal of Lightwave Technology.

[7]  C.R. Hogge.  A self correcting clock recovery circuit , 1985, IEEE Transactions on Electron Devices.

[8]  Moon-Sang Hwang,et al.  A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[9]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[10]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.