Minimum padding to satisfy short path constraints

Combinational circuits are ojlen embedded in synchronous designs with rnernory elements at the input and output ports. A performance metric for a circuit is the cycle time of the clock signal. Correct circuit operatwn requires that all paths have a delay that lies between an upper bound and a lower bound. Traditional approaches in delay optimizatwn for combinational circuits [9, 3, 6] have dealt with methods to decrease the delay of the longest path. We address the issue of satisfying the lower bound constraints. Such aproblemalso arises in wavepipelining of circuits. We propose to handle shortpath constrains as a postprocessing step after traditional delay optimization techniques. There are two issues presented in this paper. We$rst discuss necessary and su.cient conditwns for successful delay insertion without increasing delays of any longpaths. In the secondpart, we present a naive approach to padding delays (greedy heuristic) and an algorithm based on linear progratruning. We describe an applicatwn of the theory to wave pipelining of circuits. Results are presented on a set of benchmark circuits, using two delay models.