A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression

We present a programmable 80 /spl mu/W/frame (3.3 V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc). Floating-gate technology is used for on-chip kernel storage and also for performing low-power current-mode matrix multiplications. We demonstrate this IC as a front-end for JPEG compression and compare the performance of this imager to fully digital approaches.

[1]  Akira Matsuzawa,et al.  A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras , 1997, IEEE J. Solid State Circuits.

[2]  Jong-Seog Koh,et al.  An area efficient DCT architecture for MPEG-2 video encoder , 1999, IEEE Trans. Consumer Electron..

[3]  S. Oetiker,et al.  A 30-frames/s megapixel real-time CMOS image processor , 2000, IEEE Journal of Solid-State Circuits.

[4]  Suk Hwan Lim,et al.  A 10,000 Frames/s 0.18 μm CMOS Digital Pixel Sensor with Pixel-Level Memory , 2001 .

[5]  Maurizio Martina,et al.  Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming , 2002, Proceedings. IEEE International Conference on Multimedia and Expo.

[6]  Kaushik Roy,et al.  Low power reconfigurable DCT design based on sharing multiplication , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  Paul Hasler,et al.  A fully programmable CMOS block matrix transform imager architecture , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..