A virtual platform for exploring hierarchical interconnection for many-accelerator systems

The advent of many-accelerator Systems-on-Chip (SoC), as a result of the ever increasing demands for high performance and energy efficiency, has lead to the need for new interconnection schemes among the system components, which minimize the communication overhead. Towards this need, Hierarchical Networks-on-Chip (HNoCs) can provide an efficient communication paradigm for such systems: Each node is an autonomous sub-network including the hardware accelerators needed by the respective application thread, thus retaining data locality and minimizing congestion. However, HNoC design may lead to exponential increase in the design space size, due to the numerous parameter combinations of the sub-networks and the overall HNoC. In addition, the need for a prototyping framework supporting HNoC simulation with real stimuli is crucial for the accurate system evaluation. Therefore, the goal of this paper is to present (a) a SystemC framework for cycle-accurate simulation of Hierarchical NoCs, accompanied with a NoC API for node mapping on the HNoC; and (b) an exploration flow that targets to reduce the increased design space size. By using the Rician Denoising algorithm for MRI scans as a case study, the proposed DSE flow could achieve up to 2× and 1.48× time and power improvements respectively, as compared to a typical DSE flow.

[1]  Luigi Carro,et al.  Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip , 2011, NoCArc '11.

[2]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[3]  Chita R. Das,et al.  Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[4]  Dimitrios Soudris,et al.  Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging , 2014, 2014 4th International Conference on Wireless Mobile Communication and Healthcare - Transforming Healthcare Through Innovations in Mobile and Wireless Technologies (MOBIHEALTH).

[5]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Ravi Iyer.  Accelerator-rich architectures: Implications, opportunities and challenges , 2012, 17th Asia and South Pacific Design Automation Conference.

[7]  Kostas Siozios,et al.  Co-design of many-accelerator heterogeneous systems exploiting virtual platforms , 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

[8]  Jason Cong,et al.  Composable accelerator-rich microprocessor enhanced for adaptivity and longevity , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[9]  Zeljko Zilic,et al.  A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[10]  Matthias Gries,et al.  Methods for evaluating and covering the design space during early design development , 2004, Integr..

[11]  Jason Cong,et al.  Platform characterization for Domain-Specific Computing , 2012, 17th Asia and South Pacific Design Automation Conference.

[12]  Manfred Glesner,et al.  A hierarchical generic approach for on-chip communication, testing and debugging of SoCs , 2003, VLSI-SOC.

[13]  Jason Cong,et al.  Architecture support for accelerator-rich CMPs , 2012, DAC Design Automation Conference 2012.

[14]  Olivier Temam,et al.  CMA: Chip multi-accelerator , 2010, 2010 IEEE 8th Symposium on Application Specific Processors (SASP).

[15]  Jason Cong,et al.  CHARM: a composable heterogeneous accelerator-rich microprocessor , 2012, ISLPED '12.