A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS

It is challenging to design a closed-loop all-digital delay-locked loop (ADDLL) that also has a small area, low power, and fast locking for a wide frequency range operation. In this work a cyclic half-delay-line architecture with the same type of delay lines for cyclic delay deduction and coarse locking is proposed to achieve the design goals of small area and fast locking for a wide frequency range operation. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, automatic bypassing of the cyclic operation is developed to reduce power consumption for high-frequency operations. Based on these proposed techniques, a 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 closed-loop ADDLL is realized in 65-nm CMOS.

[1]  Shen-Iuan Liu,et al.  A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Liu Shen-Iuan,et al.  A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 $\mu{\hbox {m}}$ CMOS Technology , 2007, IEEE Journal of Solid-State Circuits.

[3]  Chun-Yuan Cheng,et al.  Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[4]  Shen-Iuan Liu,et al.  A wide-range and fast-locking all-digital cycle-controlled delay-locked loop , 2005, IEEE Journal of Solid-State Circuits.

[5]  Ray-Jade Chen,et al.  A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[6]  Rong-Jyi Yang,et al.  A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology , 2007, IEEE J. Solid State Circuits.

[7]  Jen-Chieh Liu,et al.  A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Andrew Allen,et al.  Dynamic frequency-switching clock system on a quad-core Itanium® processor , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Hyun-Woo Lee,et al.  A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.