Chapter 13 – Sub-RISC Processors

Publisher Summary The concurrency implementation gap is a major impediment to deploying programmable platforms. Architectures that provide poor support for application concurrency requirements make this gap wide; ad hoc methodologies for programming concurrent applications make the gap difficult to cross. Designers must address both these issues to achieve good results. First, it is important to choose a basic block processing element that can support application-specific process-level, data-level, and datatype-level concurrency. Tiny Instructionset Processors and Interconnect (TIPI) sub-RISC processing elements (PEs) are a compelling choice because they provide the right balance between programmability and application specificity. This comes at a lower cost than typical processor architectures in terms of hardware resources and designer hours. Second, designers should take a disciplined approach to deploying concurrent applications. To program the PEs, we provide a deployment methodology called Cairn that provides multiple abstractions for the different facets of the design problem. This makes it easy to cross the implementation gap. Designers can experiment with changes to the application, the architecture, and the mapping individually. Effective design space exploration will lead to high performance. The performance numbers for FPGA test case implementation show the advantages of sub-RISC PEs. Implemented in an ASIC, a multiprocessor of ClickPE and LuleaPE elements can easily surpass the IXP2800 in raw packet destination lookup performance. Clearly, the PEs can make excellent building blocks for future programmable platforms.