A new CR-delay circuit technology for high-density and high-speed DRAMs

1. h-tion With the progress in process and circuit technologies, &?ylmic RI\Ms have achieved high density and high performance. Howwer, for a suhnicmn meter device such as a 4% DRAM or beyond, it has becdifficult to realize fast operation speed by dwice size miniaturization as it used to be. This is b u s e wiring resistance and parasitic capacitance increase especially in memory cell array as the RAM density increases. Since the speed is dominate3 hy the wiring CR-delay time, the m-ry cell array operation speed cannot be fastened just by using a large size EXIS driver transistor. In the conventional peripheral circuit design, LMOS inverter chains are used to generate a necessary timing delay for controlling memory cell array operation. So the peripheral circuit speed greatly depends on supply voltage (Vcc), temperature, or several process conditions. Om the other hand, memory cell array operation speed has small dependence on these parameters. Therefore in order to ensure right operation under any operating conditions, it is necessBTy to adjust the peripheral circuit speed to the memory oell array operation in the fastest operating condition, namely high Vcc, lou temperature, and low threshold voltage (Vth) of the Ms transistor. Otherwise, an operation timing mismatch may occur between peripheral circuits and memory cell arrays. mce the timing is adjusted in the fastest condition, the peripheral circuit operation takes rwch longer time than the memory cell spray operation in the slowestlworbtl operating condition, i.e. l o w Vcc, high temperature, and high Vth, where the Ms transistor drivability is lowered. It results in a fluitleas period of time. This problem is e-ted to become =re serious as the RAM density increases. a novel CR-delay circuit teohnolom is proposed to realize high speed operation with wide operational marBin tmd minimized timing loss. It is applied to a 4Mb CMOS DRAM and the experimental results are described. significant reduction in an access time and a cmle time is aohiwed.