Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.

[1]  Giovanni Squillero,et al.  RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..

[2]  Andrea Domenici,et al.  Failure Probability and Fault Observability of SRAM-FPGA Systems , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[3]  Sergio D'Angelo,et al.  Evaluation of Single Event Upset Mitigation Schemes for SRAM based FPGAs using the FLIPPER Fault Injection Platform , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[4]  Andrea Domenici,et al.  Failure probability of SRAM-FPGA systems with Stochastic Activity Networks , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[5]  L. Sterpone,et al.  A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[6]  Massimo Violante,et al.  A new functional fault model for FPGA application-oriented testing , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[7]  William H. Sanders,et al.  The Mobius modeling tool , 2001, Proceedings 9th International Workshop on Petri Nets and Performance Models.

[8]  Cinzia Bernardeschi,et al.  Simulated Injection of Radiation-Induced Logic Faults in FPGAs , 2011 .

[9]  Cinzia Bernardeschi,et al.  A Tool for Signal Probability Analysis of FPGA-Based Systems , 2011 .

[10]  William H. Sanders,et al.  Stochastic Activity Networks: Formal Definitions and Concepts , 2002, European Educational Forum: School on Formal Methods and Performance Analysis.

[11]  Michael J. Wirthlin,et al.  The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[12]  Zdenek Kotásek,et al.  SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems , 2011, 2011 14th Euromicro Conference on Digital System Design.

[13]  Anthony Salazar,et al.  Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing , 1999 .

[14]  L. Sterpone,et al.  Analysis of the robustness of the TMR architecture in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.