A 13b 2 . 5-MHz Self-calibrated Pipelined A / D Converter in 3pm CMOS

Abstruct -While most current video applications of A/D converters require 8 b of resolution, more advanced applications will require higher resolutions. Great progress has been made in achieving 10-b resolution at video rates for HDTV using multistep flash 111, [21 and pipeline architectures [31, [41. However, certain applications such as wide dynamic range imaging require 12 b of resolution at video rates. Currently, such high-performance converters are usually implemented in hybrid technologies with precision discrete components and are very expensive. This paper describes a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques [SI. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3Cm CMOS prototype fabricated using this architecture achieves 1 3 4 resolution at 2.5 Msample/s, consumes 100 mW, and occupies 40 kmil' (26 nun2), with a single 5-V supply and two-phase nonoverlapping clock.