A 0.4–1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection

In this paper, we present a prototype ultra-fast hopping spread spectrum transceiver front-end that realizes 20 dB of processing gain in the RF before any amplification occurs along the receiver chain. This means that a narrow-band in-band interferer is rejected by 20 dB before the low noise amplifier (LNA). The correlation function at RF is made possible by using a passive mixer-first receiver architecture that is driven by an ultra-fast hopped local oscillator (LO) signal. The 47 MHop/s LO is generated using an all-digital oscillator circuit that is followed by a memoryless digital-to-analog converter (DAC). The prototype chip fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm RF CMOS process occupies 3.1 mm2 of active area. The receiver and the transmitter each consume ≈25 mW from a 1 V power supply.

[1]  James F. Buckwalter,et al.  A λ/4-lnverted N-path Filter in 45-nm CMOS SOI for Transmit Rejection with Code Selective Filters , 2018, 2018 IEEE/MTT-S International Microwave Symposium - IMS.

[2]  Hoi-Jun Yoo,et al.  A 60 kb/s–10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication , 2009, IEEE Journal of Solid-State Circuits.

[3]  Fa Foster Dai,et al.  A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC , 2006, VLSIC 2006.

[4]  Asad A. Abidi,et al.  An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[5]  Eric A. M. Klumperink,et al.  24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[6]  Ahmed M. Eltawil,et al.  Wireless field trial results of a high hopping rate FHSS-FSK testbed , 2005, IEEE Journal on Selected Areas in Communications.

[7]  H. Samueli,et al.  An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 /spl mu/m CMOS , 1995 .

[8]  Hideyuki Nosaka,et al.  A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique , 2001, IEEE J. Solid State Circuits.

[9]  Arun Natarajan,et al.  A 0.3 GHz to 1.4 GHz N-path mixer-based code-domain RX with TX self-interference rejection , 2017, 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[10]  A.G.M. Strollo,et al.  A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 $\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[11]  Ramesh Harjani,et al.  Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-$\mu$m Technology , 2011, IEEE Journal of Solid-State Circuits.

[12]  Akira Matsuzawa,et al.  A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS , 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

[13]  Xuefeng Yu,et al.  A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $\mu$m SiGe BiCMOS Technology , 2008, IEEE Journal of Solid-State Circuits.

[14]  Jacques C. Rudell,et al.  An Integrated CMOS Passive Self-Interference Mitigation Technique for FDD Radios , 2015, IEEE Journal of Solid-State Circuits.

[15]  Beomsup Kim,et al.  A 14-b direct digital frequency synthesizer with sigma-delta noise shaping , 2004, IEEE Journal of Solid-State Circuits.

[16]  Zhihe Zhou,et al.  A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  H. Samueli,et al.  An 800 MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 /spl mu/m CMOS , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[18]  Dong Yang,et al.  Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Arun Natarajan,et al.  An Interferer-Tolerant CMOS Code-Domain Receiver Based on N-Path Filters , 2018, IEEE Journal of Solid-State Circuits.

[20]  Sung-Mo Kang,et al.  A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[21]  J. S. Kenney,et al.  A PA-noise cancellation technique for next generation highly integrated RF front-ends , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[22]  R. Castello,et al.  Low power wideband receiver with RF Self-Interference Cancellation for Full-Duplex and FDD wireless Diversity , 2017, 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[23]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[24]  James F. Buckwalter,et al.  A 30.9 dBm, 300 MHz 45-nm SOI CMOS Power Modulator for Spread-Spectrum Signal Processing at the Antenna , 2018, 2018 IEEE/MTT-S International Microwave Symposium - IMS.

[25]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[26]  Gordon W. Roberts,et al.  A high-quality analog oscillator using oversampling D/A conversion techniques , 1994 .

[27]  Eric A. M. Klumperink,et al.  8-Path tunable RF notch filters for blocker suppression , 2012, 2012 IEEE International Solid-State Circuits Conference.

[28]  Ramesh Harjani,et al.  A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection , 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

[29]  Jae-Hun Jung,et al.  A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[30]  Foster F. Dai,et al.  24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 $\mu$ m SiGe BiCMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[31]  Foster F. Dai,et al.  An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC , 2010, IEEE Journal of Solid-State Circuits.