Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: and . This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.

[1]  K. Barla,et al.  Tensile Contact Etch Stop Nitride for nMOS Performance Enhancement: Influence of the Film Morphology , 2006 .

[2]  K. Yahashi,et al.  High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique , 2006, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  M. Ieong,et al.  Dual stress liner enhancement in hybrid orientation technology , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[4]  T. Noguchi,et al.  Mobility improvement for 45nm node by combination of optimized stress and channel orientation design , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[5]  K. Yamaguchi,et al.  Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  S. Shimizu,et al.  Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).