Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM

Recent advances in understanding Bias Temperature Instability (BTI) in terms of individual gate oxide defects has created a paradigm shift towards describing degradation in terms of time-dependent variability. This added time dimension to the variability analysis has proven to be a considerable design challenge. Moreover, the non-normally distributed ΔVTH shifts create compatibility issues with the current SotA statistical assessments techniques for evaluating high sigma yield of SRAM cells. Here we present a novel Non-Monte-Carlo numerical simulation methodology capable of evaluating circuit performance under workload-dependent BTI degradation.

[1]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[2]  Jae-Joon Kim,et al.  Usage-based degradation of SRAM arrays due to bias temperature instability , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[3]  Kurt Antreich,et al.  Circuit analysis and optimization driven by worst-case distances , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Andrew R. Brown,et al.  Simulation of statistical aspects of reliability in nano CMOS transistors , 2009, 2009 IEEE International Integrated Reliability Workshop Final Report.

[5]  P. Flatresse,et al.  A predictive bottom-up hierarchical approach to digital system reliability , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[6]  Francky Catthoor,et al.  Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits , 2014, IEEE Transactions on Electron Devices.

[7]  Impact of dynamic variability on SRAM functionality and performance in nano-scaled CMOS technologies , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[8]  Paul Zuber,et al.  Exponent Monte Carlo for Quick Statistical Circuit Simulation , 2009, PATMOS.

[9]  S. Rauch Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.

[10]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  Yashodhan Kanoria,et al.  Statistical static timing analysis using Markov chain Monte Carlo , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[12]  Lara Dolecek,et al.  Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[13]  A. S. Oates,et al.  Technology Scaling Effect on the Relative Impact of NBTI and Process Variation on the Reliability of Digital Circuits , 2012, IEEE Transactions on Device and Materials Reliability.

[14]  B. Kaczer,et al.  Degradation of time dependent variability due to interface state generation , 2013, 2013 Symposium on VLSI Technology.

[15]  T. Grasser,et al.  NBTI from the perspective of defect states with widely distributed time scales , 2009, 2009 IEEE International Reliability Physics Symposium.