A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End

A multimode digital front-end for EDGE, WCDMA, and WLAN modes and a WCDMA/HSDPA receiver is implemented in 0.13mum 1P6M CMOS technology occupying 5.15mm2 and dissipating 0.8/48/31 mW in EDGE/HSDPA/WLAN modes, respectively.

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