Heterogeneous Mapping to Minimize Resource Usage under Maximal Spatial Reuse Constraints for FIR-like Structures

FIR filters are vastly used in multi-mode systems where the behavior of the system changes based on user inputs or changes in the operational environment. FIR filters used for each mode of operation have different sets of parameters (coefficient sets). Partially reconfigurable FPGA platforms are shown to be viable choices to implement multi-mode filters. Joint optimization of the filters generates filters with common modules to reduce reconfiguration overhead. At physical design level, these common modules should be mapped to physical locations on the chip called Partially Reconfigurable Regions (PRRs). Furthermore depending on the availability of DSP blocks, we can implement some of these modules using DSP blocks. In this work we study the problem of reconfigurable module mapping to minimize the reconfigurable area of the filter while fully exploiting module reuse and available DSP blocks. We show that the decision problem is NP-complete and propose an ILP formulation and a heuristic to reduce the area. Our experiments show that the quality of the results of our heuristic is within 1% of the optimal result. Furthermore the results show the importance of area minimization to reduce the overall reconfiguration overhead.