论文信息 - A D2-MAC/packet Equalizer

A D2-MAC/packet Equalizer

The circuit presented in this paper is a high speed self-adaptive filter achieving equalization over a D2-MAC signal. It is build around a 16-tap transversal filter with a separate operative part computing the Gradient Algorithm and periodically updating the filter coefficients. This 130 000 transistors chip has been designed in a CMOS 1.0 ¿m technology and is at this time being used in a D2-MAC reception environment.

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