High-Level Power Estimation Methodology Applied for Processor-Level DTSE

The huge integration capability of modern technologies allows very complex systems on a single IC. The design of such ICs is a very complex task due to the challenge of managing their complexity. There are two approaches to deal with complexity. Firstly, to increase the level of abstraction by using architectural synthesis tools. Secondly, to partition these ICs into several different types of sub-designs, such as embedded microprocessors and DSPs. Figure 4. 1 gives an overview of a typical digital design flow. A behavioural VHDL description is made of the design, based on the specifications. This description is partitioned into several sub-designs, which are translated by several different architectural synthesis tools, and/or manually by a designer into a Register-Transfer level (RTL) VHDL description. The logic synthesis tool transforms the latter into a VHDL gate netlist, which is the input to layout synthesis.

[1]  Francky Catthoor.  Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions , 1998, Proceedings Design, Automation and Test in Europe.

[2]  Luca Benini,et al.  Adaptive least mean square behavioral power modeling , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[3]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[4]  Narsingh Deo,et al.  Graph Theory with Applications to Engineering and Computer Science , 1975, Networks.

[5]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[6]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[7]  Raminder Singh Bajwa,et al.  Instruction buffering to reduce power in processors for signal processing , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Hugo De Man,et al.  Efficient functional validation of system-level loop transformations for multi-media applications , 1997 .

[9]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Kees G. W. Goossens,et al.  The Petrol approach to high-level power estimation , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[11]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[12]  Farid N. Najm,et al.  Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Ibrahim N. Hajj,et al.  Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[14]  William H. Mangione-Smith,et al.  The filter cache: an energy efficient memory structure , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[15]  Wim F. J. Verhaegh,et al.  PHIDEO: High-level synthesis for high throughput applications , 1995, J. VLSI Signal Process..

[16]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[17]  David L. Kuck,et al.  The Structure of Computers and Computations , 1978 .

[18]  Damien Castelain,et al.  Digital sound broadcasting to mobile receivers , 1989 .

[19]  H. De Man,et al.  Global communication and memory optimizing transformations for low power signal processing systems , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.