An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264

An innovative self-test and self-repair technique supports built-in self-test and built-in self-repair of large embedded RAM arrays with spare rows and columns. The technique generates and analyzes the required failure bitmap information on the fly during self-test and then automatically repairs and verifies the repaired RAM arrays.

[1]  Tom Chen,et al.  Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Dilip K. Bhavsar,et al.  Testability strategy of the Alpha AXP 21164 microprocessor , 1994, Proceedings., International Test Conference.

[3]  Nany Hasan,et al.  Minimum fault coverage in reconfigurable arrays , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[4]  T.H. Lee,et al.  A 600 MHz superscalar RISC microprocessor with out-of-order execution , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  V. K. Agarwal,et al.  Built-in self-diagnosis for repairable embedded RAMs , 1993, IEEE Design & Test of Computers.

[6]  Dilip K. Bhavsar,et al.  Testability access of the high speed test features in the Alpha 21264 microprocessor , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  John Day.  A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[8]  Sy-yen Kuo,et al.  Efficient Spare Allocation for Reconfigurable Arrays , 1987, IEEE Design & Test of Computers.