Dependable Multicore Architectures at Nanoscale

This chapter introduces an overview of the main reliability threats of last nanoscale generations of CMOS technology designs. In particular, the chapter focuses on sources of process variability and their impact on circuit design and their performances, but also on the runtime variability such as voltage fluctuations as well soft errors. Further to that we go over the transistor aging provoked by different wear-out physical effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Random Telegraph Noise (RTN) and Time-Dependent Dielectric Breakdown (TDDB). 1 Reliability Issues With aggressive downscaling of CMOS technology into deep nanometer, reliability has become a major issue [1]. In this section, the general sources of reliability issues in current technology nodes are briefly explained. The sources of unreliability in current technology nodes can be categorized into three different categories: (i) variability issues, (ii) transient faults and soft errors (iii) permanent faults, all of them closely related to the fabrication process and to actual economical and physical difficulties to further improve the fabrication process [2], to the stochastic fluctuations of dopants in transistor channel and the thin oxide thickness [3] and to the intrinsic mechanisms of transistor and interconnect aging [4]. S. Kiamehr M.B. Tahoori (&) Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany e-mail: mehdi.tahoori@kit.edu S. Kiamehr e-mail: kiamehr@kit.edu L. Anghel Grenoble Institute of Technology, Phelma, Grenoble Cedex, France e-mail: lorena.anghel@imag.fr © Springer International Publishing AG 2018 M. Ottavi et al. (eds.), Dependable Multicore Architectures at Nanoscale, DOI 10.1007/978-3-319-54422-9_1 3 Due to variability, the devices/gates/circuits characteristics are different from the intended designed ones. The variability could be due to “time-zero” variation (process variation) or runtime variation such as voltage and temperature variations. Process variation is a natural device parameter variation which makes the properties of fabricated devices different from that of designed ones. In other words, due to process variation different similarly designed transistors/gates will perform (operate) with parametric differences after fabrication. Due to runtime variation, the transistors/gates properties will change (degrade) during the chip operational lifetime. Runtime variations are routed in different sources such as voltage variation and temperature variation. The voltage and temperature variations are temporal or spatial according to the place of the transistor/gate and they depend on the workload, frequency and time of operation. Therefore, they cause variation on the properties of different transistors/gates at different locations of the circuit and at different time points during the chip operational lifetime. Transistor aging is a source of runtime variations caused by different wear-out effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and soft Time-Dependent Dielectric Breakdown (soft TDDB), which in turn are dependent on process and runtime variations. All these effects cause the threshold voltage of the transistors to increase and hence the switching delay of the gates that containing these transistors increases which can eventually lead to parametric timing failures if the delay of the circuit does not meet the timing constraints. In order to deal with these sources of variation, traditional approaches consist in improving the technology process as much as possible, or to add guard-banding as a common approach at the design level. In the guard-banding approach, a timing margin is added to the designed clock cycle to guarantee the correct operation of the circuit during the operational lifetime. A pessimistic guard-banding leads to a performance loss and optimistic guard-banding results in a low reliability of the chip. Therefore, the required timing margin needs to be accurately predicted. Figure 1 shows the components of the required timing margin for IBM Power7+ processor [5]. As shown in this figure, the main components of the timing margin are uncertainty (e.g. global and local process variation), wearout (transistor aging) and voltage and thermal variations. Fig. 1 Components of chip guard-band for the IBM Power7+ [5] 4 S. Kiamehr et al.