A framework for reconfigurable computing: task scheduling and context management

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.

[1]  Ranga Vemuri,et al.  Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[2]  Román Hermida,et al.  A framework for scheduling and context allocation in reconfigurable computing , 1999, Proceedings 12th International Symposium on System Synthesis.

[3]  Scott Hauck,et al.  Configuration prefetch for single context reconfigurable coprocessors , 1998, FPGA '98.

[4]  Wayne Luk,et al.  Compilation tools for run-time reconfigurable designs , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[5]  Ranga Vemuri,et al.  An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[6]  Milan Vasilko,et al.  Architectural Synthesis Techniques for Dynamically Reconfigurable Logic , 1996, FPL.

[7]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[8]  Vivek Sarkar,et al.  Space-time scheduling of instruction-level parallelism on a raw machine , 1998, ASPLOS VIII.

[9]  Dinesh Bhatia,et al.  RACE: Reconfigurable and Adaptive Computing Environment , 1996, FPL.

[10]  E. Tau,et al.  A First Generation DPGA implementation , 1995 .

[11]  Maya Gokhale,et al.  NAPA C: compiling for a hybrid RISC/FPGA architecture , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[12]  Fadi J. Kurdahi,et al.  Kernel scheduling in reconfigurable computing , 1999, DATE '99.

[13]  Steven W. K. Tjiang,et al.  SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.

[14]  David Robinson,et al.  New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic , 1998, FPL.

[15]  Bruce A. Draper,et al.  Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems , 1999, ICVS.

[16]  Ranga Vemuri,et al.  An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures , 1998, IPPS/SPDP Workshops.

[17]  John Wawrzynek,et al.  Instruction-Level Parallelism for Reconfigurable Computing , 1998, FPL.

[18]  Ranga Vemuri,et al.  An effective design system for dynamically reconfigurable architectures , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[19]  Dinesh Bhatia,et al.  Temporal partitioning and scheduling for reconfigurable computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[20]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[21]  Ranga Vemuri,et al.  Optimal temporal partitioning and synthesis for reconfigurable architectures , 1998, Proceedings Design, Automation and Test in Europe.

[22]  André DeHon,et al.  MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[23]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Re-configurable Architecture , 2000 .

[24]  John J. Granacki,et al.  DEFACTO: A Design Environment for Adaptive Computing Technology , 1999, IPPS/SPDP Workshops.

[25]  Vivek Sarkar,et al.  Baring it all to Software: The Raw Machine , 1997 .