A host-network interface architecture for ATM

The AURORA testbcd wifl include ATM switches that are capable of handling traffic at speedsof 622 Mbit/sec. To load this network with data at such a speed, a host-network interfaee is required. Such art interfaee must both move data at the speed of the network and convert it between the network format (ATM cells) and a format useful to the host (e.g. transport level packets). A novel architecture for such an interface, which combines high speed with a high degree of flexibility, is described. The interfaee consists of one embedded controller per direction to decide where data should be fetched from and stored, and dedicated hardware to effect the moving and formatting of data. Alternative memory architectures are proposed, the choice between them being dependent on the type of bus in the host. The flexible design will allow experimentation with a variety of scheduling and segmentationheass embly rdgorithms, and with new transport protocols.