A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.

[1]  Yuan-Hao Huang,et al.  A sub-word parallel digital signal processor for wireless communication systems , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[2]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[3]  Young-Su Kwon,et al.  MDSP-II: a 16-bit DSP with mobile communication accelerator , 1999 .

[4]  Y. Naito,et al.  An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[5]  Sivanand Simanapalli,et al.  DSP16000: a high performance, low-power dual-MAC DSP core for communications applications , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[6]  P. Groves,et al.  A 600 MHz VLIW DSP , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  Mark A. Richards.  On hardware implementation of the split-radix FFT , 1988, IEEE Trans. Acoust. Speech Signal Process..

[8]  F. Lange,et al.  A 4.32 GOPS 1 W general-purpose DSP with an enhanced instruction set for wireless communication , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[9]  Theodore S. Rappaport,et al.  Wireless communications - principles and practice , 1996 .

[10]  Yuan-Hao Huang,et al.  Design of an OFDM receiver for high-speed wireless LAN , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[11]  Ruby B. Lee.  Multimedia extensions for general-purpose processors , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[12]  Alvin M. Despain,et al.  Very Fast Fourier Transform Algorithms Hardware for Implementation , 1979, IEEE Transactions on Computers.

[13]  Apostolis K. Salkintzis,et al.  ADC and DSP challenges in the development of software radio base stations , 1999, IEEE Wirel. Commun..

[14]  E. Sackinger,et al.  A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP , 2000, IEEE Journal of Solid-State Circuits.

[15]  Ingrid Verbauwhede,et al.  A Low Power DSP Engine for Wireless Communications , 1998, J. VLSI Signal Process..

[16]  Liang-Gee Chen,et al.  A digital signal processor with programmable correlator array architecture for third generation wireless communication system , 2001 .

[17]  J. Fridman.  Sub-word parallelism in digital signal processing , 2000 .

[18]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[19]  K. Ronner,et al.  A 1.3 GOPS parallel DSP for high performance image processing applications , 2000, Proceedings of the 25th European Solid-State Circuits Conference.

[20]  Hsi-Pin Ma,et al.  An Uplink Baseband Receiver architecture and FPGA Implementation for W-CDMA Systems , 2000 .