A derotator VLSI which removes the frequency and phase errors of a received signal in digital receivers was developed using a CORDIC algorithm. The CORDIC circuit directly rotates the input signal according to the phase error information, thus is much simpler than the conventional derotator architecture which consists of a DDFS (Direct Digital Frequency Synthesizer) and a complex multiplier. In order to improve the operating speed without employing the pipelining, a fast direction sequence generation method that exploits the linearity of the tangent function in small angles is utilized. The newly employed direction sequence generation method needs only about a third of the iterative computations when compared with the conventional CORDIC algorithm. The chip was designed and implemented using a 0.6 /spl mu/m triple metal CMOS process by the full custom layout method. The whole chip size is 6.8 mm/sup 2/ and the operating frequency which is higher than 25 MHz is achieved.
[1]
C. Chien,et al.
Computer-aided design of a BPSK spread-spectrum chip set
,
1992
.
[2]
Y.H. Hu,et al.
CORDIC-based VLSI architectures for digital signal processing
,
1992,
IEEE Signal Processing Magazine.
[3]
R. J. van de Plassche,et al.
A 540-MHz 10-b polar-to-Cartesian converter
,
1991
.
[4]
H. Samueli,et al.
A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance
,
1991
.
[5]
H. Samueli,et al.
A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications
,
1991
.
[6]
Wonyong Sung,et al.
A fast direction sequence generation method for CORDIC processors
,
1997,
1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[7]
H. Samueli,et al.
A 200 MHz quadrature digital synthesizer/mixer in 0.8 /spl mu/m CMOS
,
1995
.