Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

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