Synthesis of low-cost parity-based partially self-checking circuits

A methodology for the synthesis of partially self-checking multilevel logic circuits with low-cost parity-based concurrent error detection (CED) is described. A subset of the inputs of the circuit is selected to realize a simple characteristic function such that CED is disabled whenever the inputs belong to the OFF-set of the characteristic function. This don't-care space in the operation of the CED circuitry is used to optimize the CED circuitry during synthesis. It is shown that this methodology is very effective at targeting faults with a high sensitization probability. Experimental results show that the proposed approach, which is of special interest in applications where a low-cost CED solution is desired, achieves a significant reduction in the error rate in logic circuits.

[1]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[2]  Bella Bose,et al.  A self-checking ALU design with efficient codes , 1996, Proceedings of 14th VLSI Test Symposium.

[3]  Fabio Somenzi,et al.  Logic synthesis and verification algorithms , 1996 .

[4]  Johan Karlsson,et al.  On latching probability of particle induced transients in combinational networks , 1994, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing.

[5]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[6]  Dhiraj K. Pradhan,et al.  Fault-tolerant computing : theory and techniques , 1986 .

[7]  Edward J. McCluskey,et al.  Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  John F. Wakerly,et al.  Error detecting codes, self-checking circuits and applications , 1978 .

[9]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[10]  Michael Nicolaidis,et al.  Automatic generation algorithms, experiments and comparisons of self-checking PLA schemes using parity codes , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[11]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[12]  James E. Smith,et al.  Strongly Fault Secure Logic Networks , 1978, IEEE Transactions on Computers.