A fault-simulation-based approach for logic diagnosis

This paper presents a logic diagnosis approach performed in two phases, (i) a fault localization phase searching in to the dictionary a set of suspected lines able to explain the observed errors, and (ii) a fault model allocation phase associating a set of fault models on each suspect identified in the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic). Experimental results on full scan circuits show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

[1]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[2]  Arnaud Virazel,et al.  DERRIC: A Tool for Unified Logic Diagnosis , 2007, 12th IEEE European Test Symposium (ETS'07).

[3]  Leendert M. Huisman.  Diagnosing arbitrary defects in logic designs using single location at a time (SLAT) , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Irith Pomeranz.  On pass/fail dictionaries for scan circuits , 2001, Proceedings 10th Asian Test Symposium.

[5]  Srikanth Venkataraman,et al.  Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..

[6]  Premachandran R. Menon,et al.  Critical Path Tracing - An Alternative to Fault Simulation , 1983, 20th Design Automation Conference Proceedings.

[7]  Hans-Joachim Wunderlich,et al.  Adaptive Debug and Diagnosis without Fault Dictionaries , 2007, ETS.

[8]  R. D. Blanton,et al.  A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior , 2006, 2006 IEEE International Test Conference.

[9]  Kazuki Shigeta,et al.  An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Alberto Bosio,et al.  SoC Symbolic Simulation: a case study on delay fault testing , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[11]  Tracy Larrabee,et al.  Multiplets, models, and the search for meaning: improving per-test fault diagnosis , 2002, Proceedings. International Test Conference.

[12]  Andreas G. Veneris,et al.  Incremental fault diagnosis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Giorgio Di Natale,et al.  LIFTING: A Flexible Open-Source Fault Simulator , 2008, 2008 17th Asian Test Symposium.