论文信息 - Automatic design and partitioning of systolic/wavefront arrays for VLSI - 字舞流文

Automatic design and partitioning of systolic/wavefront arrays for VLSI

E. Deprettere | H. Nélis | H. Nelis

[1] Thomas Kailath,et al. Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[2] H. Nelis,et al. Automatic Design And Partitioning Of VLSI Systolic/Wavefront Arrays , 1987, Optics & Photonics.

[3] Sun-Yuan Kung,et al. Timing Analysis and Design Optimization of VLSI Data Flow Arrays , 1986, ICPP.

[4] Benjamin W. Wah,et al. Systematic approaches to the design of algorithmically specified systolic arrays , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[5] D. V. Bhaskar Rao,et al. Wavefront Array Processor: Language, Architecture, and Applications , 1982, IEEE Transactions on Computers.

[6] H. T. Kung,et al. Systolic Arrays for (VLSI). , 1978 .

[7] Dan I. Moldovan,et al. Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays , 1986, IEEE Transactions on Computers.