An innovative free memory design for network processors in home network gateway

With the fast development of digital home network, the bandwidth demands of home network gateway is growing rapidly. The memory bandwidth has become the main performance bottleneck of network processor. Open-page policy and linear allocation approach have been proposed to improve the throughput of network processor through utilizing peak bandwidth of DRAM. Yet, in IC design, due to limitation of linked list memory management and IC area, the implementation of linear allocation is more complex. In this paper, a novel bitmap approach is proposed for free memory management. With efficient search architecture, compression algorithm and pre-fetch buffer, the work complexity of bitmap approach can be reduced considerably, linear allocation can be implemented easily, and memory management can also be optimized to provide high effectiveness.

[1]  Matthias Gries,et al.  Algorithm architecture trade offs in network processor design , 2001 .

[2]  Chantal Ykman-Couvreur,et al.  System-level performance optimization of the data queueing memory management in high-speed network processors , 2002, DAC '02.

[3]  Albert G. Greenberg,et al.  Hardware-efficient fair queueing architectures for high-speed networks , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[4]  R. Wilder,et al.  Wide-area Internet traffic patterns and characteristics , 1997, IEEE Netw..

[5]  Nicholaos Zervos,et al.  A fully programmable memory management system optimizing queue handling at multi gigabit rates , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Kurt Keutzer,et al.  Comparing analytical modeling with simulation for network processors: a case study , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Tong Liu,et al.  Design of an efficient memory subsystem for network processor , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[8]  T. N. Vijaykumar,et al.  Efficient use of memory bandwidth to improve network processor throughput , 2003, ISCA '03.

[9]  Manolis Katevenis,et al.  Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques , 2001, ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240).

[10]  Eric Wolman,et al.  A Fixed Optimum Cell-Size for Records of Various Lengths , 1965, JACM.

[11]  Abhijit K. Choudhury,et al.  New implementation of multi-priority pushout for shared memory ATM switches , 1996, Comput. Commun..

[12]  Daein Jeong,et al.  Design of a Generalized Priority Queue Manager for ATM Switches , 1997, IEEE J. Sel. Areas Commun..