Influence of bit line twisting on the faulty behavior of DRAMs

Bit line twisting is an effective design method commonly used to reduce the impact of bit line coupling noise in high density memory devices. This paper investigates the way bit line twisting influences the faulty behavior of DRAMs, based on an analytical evaluation of coupling effects on the one hand, and a simulation-based fault analysis using a Spice simulation model on the other. Two different DRAM twisting schemes, in addition to a third untwisted bit line scheme, are presented and analyzed. Both the analytical and the simulation-based evaluation results show that each scheme has its own specific impact on the faulty behavior. The same approach presented in the paper can be used to analyze the impact of other bit line twisting schemes on the memory faulty behavior.

[1]  Ad J. van de Goor,et al.  Consequences of RAM bitline twisting for test coverage , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Said Hamdioui,et al.  Effects of bit line coupling on the faulty behavior of DRAMs , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[3]  Hideto Hidaka,et al.  Twisted bit-line architectures for multi-megabit DRAMs , 1989 .

[4]  Kiyoo Itoh,et al.  Vlsi Memory Chip Design , 2006 .

[5]  Bruce F. Cockburn,et al.  An investigation into crosstalk noise in DRAM structures , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[6]  Kiyoo Itoh,et al.  A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure , 1988 .

[7]  John K. DeBrosse,et al.  The evolution of IBM CMOS DRAM technology , 1995, IBM J. Res. Dev..

[8]  Ad J. van de Goor,et al.  Approximating infinite dynamic behavior for DRAM cell defects , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).