A 21st Century Approach to Electronic Device Reliability

Lifetime prediction for device operation has usually relied on accelerated testing at elevated temperature and then extrapolation back to room temperature operation. This technique frequently fails for scaled, high current density devices found in modern technologies. Device failure is driven by electric field or current mechanisms or low activation energy processes that are masked by other mechanisms at high temperature. Device degradation can be driven by failure in either active structures or passivation layers. We have seen that many issues have an affect on compound semiconductor performance and reliability, including the material quality, strain state, surface cleaning process, and the actual voltage and current conditions during aging. We have conducted comprehensive plan of reliability engineering for III-V device structures. This includes materials and electrical characterization and reliability testing. These techniques were utilized to develop new simulation technologies for device operation and reliability. This allows accurate prediction not only of reliability, but the ability to design structures specifically for improved reliability of operation. Our intensely integrated approach of utilizing new characterization methods, device simulations and realistic device stressing and aging provided new insights into device failure mechanisms. DISTRIBUTION A: Distribution approved for public release. 1. Reliability Test Station In order to accomplish the goal of creating new methods for optically and electrically characterizing and stressing semiconductor devices, an in-house design from readily available, off-the shelf parts such as power supplies and data-acquisition and control equipment was created. The system was designed for maximum flexibility in order to provide long term voltage/current/temperature stress testing, characteristic IV plots, gate pulse testing and also incorporated laser and shutter control for optical pumping from different laser sources. DCstress test measurements are taken every second and stored at a user-defined interval (minimum of a second) in a SQL database for future analysis, whereas characterization tests require data points to be measured and stored. An intuitive and accessible user interface is necessary for any level of flexibility. I-V plots, shown in Figure 1, and DC stress results, shown in Figure 2, are displayed graphically and in real-time. Details of this system design can be found in [Cheney 2012] (available on-line at http://ufdc.ufl.edu/UFE0044885/00001) . High-speed, high-voltage configuration The high-speed, high-voltage variation shown in Figure 3 displays the hardware, comprised of two power supplies, a pico-ammeter, and a USB oscilloscope. This combination of the different commercially available off-the-shelf instruments creates a robust system with accurate measurement, large bias-voltages, and high-speed measurement. All voltage measurements are made directly by the USB oscilloscope and can handle voltages as high as ±80 volts. During long term DC stress tests, the system samples every second so it takes advantage of the higher precision 16-bit sampling. This wider sampling precision is also applied during characterization measurements since the sample speed is dependent on how quickly the power supplies can sweep voltages and not on sample-rate of the measurement. When performing gate-lag tests with a narrow gate pulse (1 μs), the USB scope samples at the maximum speed (up to 50MHz) using the reduced sample precision to 12 bits. The 50MHz sample rate enables the gate pulse widths to decrease by orders of magnitude into the nanosecond pulse width range. Long-term test configuration The long-term test set can stress four devices at a time. This setup does not have all the capabilities of the high-speed, high-voltage set, lacking high-voltage gate control with a ±10 volt range and also the data acquisition is limited to 50k samples per second. Figure 4 shows the hardware, comprised of an Instek DC power supply for the drain bias, a National Instruments (NI) analog output module serving as the gate bias supply, an NI high-voltage input module (±60 volt) that measures the drain voltage, and an NI input module to read gate voltages, gate current and the drain current measurement. Optical pumping configuration The optical pumping station, shown in Figure 5, has a unique requirement to stream continuously at high speeds. This requirement precludes the data acquisition equipment in the long-term station because the TDM sampling is too slow. The USB oscilloscope in the highspeed, high-voltage station is not able to stream continuously and sacrifices too much precision to sample fast enough. The compromise is the NI USB-6366 that has 16-bit simultaneous DISTRIBUTION A: Distribution approved for public release. sampling up to 2 MHz. It uses the Instek power supply as the drain bias source. The NI USB6366 has digital output controls that are used to switch shutters on the different lasers. Probe station configuration The probe station, Figure 6, is a version of the high-speed, high-voltage configuration without the gate pulsing capabilities, using a USB oscilloscope for data acquisition. The voltage inputs VD and VG are connected to probes on a probe station, allowing unpackaged parts to be tested on the system. Figure 1 Software user interface showing I-V plots DISTRIBUTION A: Distribution approved for public release. Figure 2. Software GUI showing DC stress DISTRIBUTION A: Distribution approved for public release. Figure 3. High-speed, high-voltage test station Figure 4. Long term test station DISTRIBUTION A: Distribution approved for public release. Figure 5. Optical pumping configuration Figure 6. Probe station configuration DISTRIBUTION A: Distribution approved for public release. Section 2. Device Testing – bias and temperature stressing Devices from two different vendors were used in this study. Eighteen HEMTs and six transmission line modules (TLM) from the Air Force Research Labs (AFRL) underwent accelerated aging. In addition, there were two devices from an undisclosed vendor, called vendor A. AFRL Devices The HEMT layer structures used in these experiments were grown by metal-organic chemical vapor deposition (MOCVD) on 6H SiC semi-insulating substrates with an unintentionally doped 3nm GaN cap, 15nm Al0.28Ga0.72N barrier and 2.25μm Fe-doped GaN buffer. Plasma enhanced chemically vapor deposited SiN was used for device passivation. The HEMTs had dual submicron Ni/Au gates with dimensions of 0.125, 0.14 or 0.17 x 150 μm. The HEMTs employed a Ti/Al/Ni/Au Ohmic metallization with a gate periphery of 300 μm, sourceto-gate and gate-to-drain distances of 2 μm with SiNx passivation. The devices were packaged and wire-bonded for testing. The initial quality of the devices varied widely, with less than 20% actually being suitable for stressing post-packaging. Pre-stress device screening removed parts whose gate leakage was above 0.5 μA or with drain leakage more than 500 μA. The devices underwent accelerated aging by DC-stressing at 1500C at three different bias points along the one-watt load curve, shown in Figure 7: VG = 0 (on-state), VG = -2 (semi-on), VG < VTH (off-state). The bias points were chosen with the expectation of devices stressed in the onstate mostly experiencing stress on the channel, while gate defects would manifest themselves as VG approaches pinch-off and VDG approaches the device’s critical voltage [del Alamo 2009]. Devices that are biased between the on-state and off-state experience stress on both the channel and the gate. Since a gate bias of VG = -2 is closer to the operating point of a transistor in a circuit, and because this bias point has the potential to show more interesting results, most of the devices are stressed under this bias condition. To maintain a constant power-dissipation of one watt in the channel, VD was adjusted based on the measured ID, except in the off-state case, where VD was set to constant voltage The stress tests were interrupted when either a 10% change in the drain current or an order of magnitude change in gate current were observed. The devices tended to fail in one of two ways, either an abrupt sharp drop in drain current (ΔID > 10%) or a gradual decline in this current. Figure 8 is representative of both types of degradation over time. Abrupt failures Table 1 lists the devices that failed abruptly. Figure 9 shows the typical characteristic results of a device that failed abruptly. The dc characteristics show little to no change as a result of the DC-stress test. This suggests the degradation observed was possibly due to contact degradation. Since contact failure has been shown to be temperature dependent [Meneghesso 2008] [Douglas 2011] and to further support the hypothesis that this is contact failure, the fluctuations in current reduced dramatically as the test base-plate temperature was lowered. At a lower base-plate temperature, the devices appear to behave normally, however, they do experience a second abrupt drop in channel current once stress continues. DISTRIBUTION A: Distribution approved for public release. Gradual failures Table 2 lists the conditions and devices that displayed a gradual failure mechanism. Most all of the devices that did not exhibit the abrupt drop in current drop, tended to have a similar degradation pattern to that shown in Figure 8-B, with an initial drop in drain current for the first 10 minutes. This has been suggested as resulting from the device reaching a new steady-state as trapping and de-trapping reach equilibrium [del Alamo 2009]. In several of the devices, the current increased before gradually declining to the 10% threshold where the test stopped. Figure 10 shows the typical pre and post electrical characteristic I-V plots, which are indicative of permanent degradation. It is interesting to note that the gate pulse transconductance plot shows no change in the