Highly stable 65 nm node (CMOS5) 0.56 /spl mu/m/sup 2/ SRAM cell design for very low operation voltage

We show very high density embedded 6T-SRAM cell of 0.56 /spl mu/m/sup 2/. This is the smallest value reported so far. Developed embedded SRAM cell achieves adequate SNM of 90 mV at 0.6 V on high performance 65 nm SoC platform (CMOS5).