A Testable PLA Design with Low Overhead and High Fault Coverage

A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.

[1]  Hideo Fujiwara,et al.  A Design of Programmable Logic Arrays with Universal Tests , 1981, IEEE Transactions on Computers.

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  An Algorithm for Optimal PLA Folding , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Kozo Kinoshita,et al.  A Design of Programmable Logic Arrays with Universal Tests , 1981, IEEE Transactions on Computers.

[4]  Alberto Sangiovanni-Vincentelli,et al.  Techniques for Programmable Logic Array Folding , 1982, DAC 1982.

[5]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[6]  Roy A. Wood.  A High Density Programmable Logic Array Chip , 1979, IEEE Transactions on Computers.

[7]  Kozo Kinoshita,et al.  An Easily Testable Design of Programmable Logic Arrays for Multiple Faults , 1983, IEEE Transactions on Computers.