In this paper we demonstrate the fastest CMOS circuits reported to date. At room temperature the unloaded CMOS inverter delay as low as 7.85 psec is measured. This number drops to 5.5 psec at liquid nitrogen temperature. The devices used in the study are built on SOI, with excellent short-channel characteristics down to 0.06 /spl mu/m for the NFETs and 0.08 /spl mu/m for the PFETs. Although devices with high threshold voltages are used, record delays are achieved at relatively low supply voltages. At 1.8 V, the inverter delay is 8.3 psec and 5.9 psec at T=300 K and T=80 K, respectively. The corresponding delays at 1.2 V are 11.4 psec and 8.2 psec. Through proper device optimization, we demonstrate that undesired SOI floating-body effects are minimized as well. These results demonstrate that there is significant room for continued performance enhancement in scaled CMOS.