MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

Modern Field Programmable Gate Arrays (FPGAs) embed dedicated blocks for Memories (BRAMs), digital signal processing (DSPs) and hardwired microprocessors merged with the reconfigurable logic array. This trend, coupled with Error Correction Code (ECC) mechanism and Dynamic Partial Reconfiguration (DPR), makes these devices ideal candidates for mission critical applications where high reliability is a strict requirement. Therefore, efficient and in-field testing became a major concern. Unfortunately, typical on-line memory testing approaches are not fully optimized for the reconfigurable scenario. In fact, a suitable fault model should be considered in order to enhance the fault coverage and reduce the test redundancy. In this work, we proposed the MATS** algorithm, which is able to reduce the execution time and optimize the fault coverage with respect to most popular embedded memories March Tests. Furthermore, MATS** results to be highly suitable to be executed, even partially, in brief time slots available within the device mission. Experimental results show that our approach is around 30% faster than state-of-the-art solutions while achieving the optimal fault coverage.

[1]  Andreas Steininger,et al.  A transparent online memory test for simultaneous detection of functional faults and soft errors in memories , 2003, IEEE Trans. Reliab..

[2]  Masayuki Sato,et al.  Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD) , 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

[3]  Ludovica Bozzoli,et al.  Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach , 2018, ARC.

[4]  Charles E. Stroud,et al.  BIST-based diagnosis of FPGA interconnect , 2002, Proceedings. International Test Conference.

[5]  Luca Sterpone,et al.  A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing , 2013, IEEE Transactions on Computers.

[6]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  A. W. Ruan,et al.  A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA , 2014, 2014 International Symposium on Integrated Circuits (ISIC).

[8]  Luca Sterpone,et al.  Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[9]  Charles E. Stroud,et al.  Built-In Self-Test of embedded memory cores in Virtex-5 Field Programmable Gate Arrays , 2011, 2011 IEEE 43rd Southeastern Symposium on System Theory.

[10]  Ludovica Bozzoli,et al.  COMET: a Configuration Memory Tool to Analyze, Visualize and Manipulate FPGAs Bitstream , 2018 .