Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.

[1]  Yiran Chen,et al.  A novel architecture of the 3D stacked MRAM L2 cache for CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[2]  Weisheng Zhao,et al.  Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions , 2012, IEEE Transactions on Electron Devices.

[3]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Claude Chappert,et al.  Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ) , 2009, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.

[5]  J Joshua Yang,et al.  Memristive devices for computing. , 2013, Nature nanotechnology.

[6]  Shih-Hung Chen,et al.  Phase-change random access memory: A scalable technology , 2008, IBM J. Res. Dev..

[7]  A. Fert,et al.  The emergence of spin electronics in data storage. , 2007, Nature materials.

[8]  Zhaohao Wang,et al.  An overview of spin-based integrated circuits , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).