High-Level Synthesis for Low Power

High-level synthesis (also called behavioral synthesis or architectural synthesis) refers to the process of transforming a functional or behavioral specification of a design into a structural RTL implementation. A typical high-level synthesis process involves several subtasks including behavioral transformations, module selection, clock period selection, scheduling, and resource sharing, and RTL circuit generation. High-level synthesis has a large impact on power consumption, which, if properly exploited, can lead to large power savings. This chapter analyzes the effect of various high-level synthesis subtasks on power, and presents various techniques that can be used to optimize power consumption during high-level synthesis.