Chip parasitic extraction and signal integrity verification (extended abstract)

In was projected by the National TechnologyRoadmap for Semiconductors that by the year 1998 thefeature size will shrink to 0.25¿m and the chips maycontain as many as 28 million transistors.As the widthof wires shrinks, resistance increases more rapidly thancapacitance decreases.As the result, interconnect contributes50% of total delay in 0.35¿m technology andis expected to contribute up to 70% in 0.25¿m.Interconnectdelay on chip dominates the gate delay.Largeheight to width ratio, 2:1 in 1998 and 2.5:1 in 2001,and many interconnect layers, 5-8 in 1998 and 8-10 in2001, make lateral coupling increasingly more significantthan coupling to ground.Cross talk not only causes awrong logic result on one particular clock cycle, but alsoleads to a different timing behavior of neighboring lines.Delay cannot be calculated accurately without takingcross talk into account.Not to mention conformal dielectricsand non-orthogonal conductor cross sections.The above technology shift calls for 3D parasitic extraction.However, it is prohibitively expensive to extractevery net in 3D; in fact, it is not necessary to do so.Beforepresenting the multi-tiered extraction methodology,I will first classify various extracion methodologies.