PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this article, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit-sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the computational efficiency. The experimental results show that our proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.

[1]  Kurt Antreich,et al.  Circuit analysis and optimization driven by worst-case distances , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Lihong Zhang,et al.  Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  G. Gielen,et al.  The Generalized Boundary Curve A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits , 2002 .

[4]  Francisco V. Fernández,et al.  A two-step layout-in-the-loop design automation tool , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[5]  Helmut E. Graeb,et al.  Constraint-Based Layout-Driven Sizing of Analog Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Ricardo Povoa,et al.  AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation , 2015, 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[7]  Lihong Zhang,et al.  Lithography-Aware Analog Layout Retargeting , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Puneet Gupta,et al.  Wafer Topography-Aware Optical Proximity Correction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Mohamed Dessouky,et al.  Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Majid Sarrafzadeh,et al.  Vlsi Circuit Layout , 1999 .

[11]  Yu-Hsuan Su,et al.  Fast Lithographic Mask Optimization Considering Process Variation , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Juan Andrés,et al.  Integrated circuit layout design methodology for deep sub-wavelength processes , 2005 .

[13]  Mohamed Dessouky,et al.  Incremental layout-aware analog design methodology , 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

[14]  Zheng Liu,et al.  A performance-constrained template-based layout retargeting algorithm for analog integrated circuits , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[15]  Chien-Nan Jimmy Liu,et al.  A layout-aware automatic sizing approach for retargeting analog integrated circuits , 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

[16]  Lihong Zhang,et al.  Analog Integrated Circuit Sizing and Layout Dependent Effects: A Review , 2014 .

[17]  David Bol,et al.  Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools , 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

[18]  Rob A. Rutenbar,et al.  WiCkeD: Analog Circuit Synthesis Incorporating Mismatch , 2002 .

[19]  Jingyu Wang,et al.  Hybrid OPC flow with pattern search and replacement , 2015, Advanced Lithography.

[20]  David Z. Pan,et al.  MOSAIC: Mask optimizing solution with process window aware inverse correction , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[21]  Arthur Tay,et al.  Performance-Based Optical Proximity Correction Methodology , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Yih-Lang Li,et al.  Intelligent optical proximity correction using genetic algorithm with model- and rule-based approaches , 2009 .

[23]  K. J. Antreich,et al.  Nominal design of integrated circuits on circuit level by an interactive improvement method , 1988 .

[24]  A. Seoud,et al.  Introducing process variability score for process window OPC optimization , 2009, Photomask Technology.

[25]  Lihong Zhang,et al.  Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[26]  Gonzalo R. Arce,et al.  Computational Lithography , 2010, Wiley series in pure and applied optics.