Energy-Efficient Design Methodologies: High-Performance VLSI Adders

Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, we developed adder topology yielding up to 20% performance improvement and 4.5× energy reduction over existing designs.

[1]  Borivoje Nikolic,et al.  Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example , 2009, IEEE Journal of Solid-State Circuits.

[2]  M. Horowitz,et al.  Managing wire scaling: a circuit perspective , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[3]  Bart R. Zeydel,et al.  Energy-Delay Characteristics of CMOS Adders , 2006 .

[4]  Bart R. Zeydel,et al.  Energy optimization of pipelined digital systems using circuit sizing and supply scaling , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Victor V. Zyuban,et al.  Balancing hardware intensity in microprocessor pipelines , 2003, IBM J. Res. Dev..

[6]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[7]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[8]  Shmuel Winograd,et al.  On the Time Required to Perform Addition , 1965, JACM.

[9]  Vojin G. Oklobdzija,et al.  High-performance energy-efficient microprocessor design , 2006 .

[10]  M. Lehman,et al.  Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units , 1961, IRE Trans. Electron. Comput..

[11]  Orest J. Bedrij.  Carry-Select Adder , 1962, IRE Trans. Electron. Comput..

[12]  Robert W. Doran.  Variants of an Improved Carry Look-Ahead Adder , 1988, IEEE Trans. Computers.

[13]  Giorgos Dimitrakopoulos,et al.  High-speed parallel-prefix VLSI Ling adders , 2005, IEEE Transactions on Computers.

[14]  Dursun Baran,et al.  Exploration of switching activity behavior of addition algorithms , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[15]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[16]  Bart R. Zeydel,et al.  Efficient mapping of addition recurrence algorithms in CMOS , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

[17]  Jaehong Park,et al.  470ps 64bit Parallel Binary Adder , 2000 .

[18]  J. Petrovick,et al.  The circuit and physical design of the POWER4 microprocessor , 2002, IBM J. Res. Dev..

[19]  R.W. Brodersen,et al.  Methods for true energy-performance optimization , 2004, IEEE Journal of Solid-State Circuits.

[20]  Vojin G. Oklobdzija,et al.  Some optimal schemes for ALU implementation in VLSI technology , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[21]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[22]  Dursun Baran,et al.  Switching activity calculation of VLSI adders , 2009, 2009 IEEE 8th International Conference on ASIC.

[23]  Mark Horowitz,et al.  Robust Energy-Efficient Adder Topologies , 2007, 18th IEEE Symposium on Computer Arithmetic (ARITH '07).

[24]  Sanu Mathew,et al.  Energy-delay estimation technique for high-performance microprocessor VLSI adders , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[25]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[26]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[27]  Sanu Mathew,et al.  Comparison of high-performance VLSI adders in the energy-delay space , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  R. Krishnamurthy,et al.  A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[29]  Huey Ling.  High Speed Binary Adder , 1981, IBM J. Res. Dev..

[30]  Sanjeev Saxena,et al.  On Parallel Prefix Computation , 1994, Parallel Process. Lett..