Fault behavior dictionary for simulation of device-level transients

The paper presents a methodology for the simulation of massive number of device-level transient faults. Fault injection locations and the gate around those locations are extracted and evaluated with SPICE. The extracted sub-circuits are exercised exhaustively while fault-injections are performed. Faulty behavior at the outputs of each sub-circuit is recorded in a dictionary, along with the associated input vector, fault-injection time, and location. The recorded logical errors are injected concurrent transient simulator is developed to allow simultaneous evaluation of a massive number of fault-injections, in a single simulation pass. The methodology is illustrated by a case study of MC68000 microprocessor.

[1]  Andrew B. Kahng,et al.  A new class of iterative Steiner tree heuristics with good performance , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  T. Sakurai,et al.  Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.

[3]  J.-H. Kong,et al.  A mixed-level MOS logic simulator utilizing a new continuous strength algebra (CSAL) , 1990, Ninth Annual International Phoenix Conference on Computers and Communications. 1990 Conference Proceedings.

[4]  W.F.J. Verhaegh,et al.  Flexible datapath compilation for Phideo , 1991, Euro ASIC '91.

[5]  H. De Man,et al.  Silicon integration of digital user-end mobile communication systems , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[6]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[7]  N. P. van der Meijs,et al.  An Efficient Finite Element Method for Submicron IC Capacitance Extraction , 1989, 26th ACM/IEEE Design Automation Conference.

[8]  M Chiang,et al.  LCC simulators speed development of synchronous hardware , 1986 .

[9]  Takeshi Yoshimura,et al.  GRAPH THEORETICAL COMPACTION ALGORITHM. , 1985 .

[10]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[11]  David G. Luenberger,et al.  Linear and nonlinear programming , 1984 .

[12]  J. Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[13]  R. Harrington.  Matrix methods for field problems , 1967 .

[14]  Chi-Yuan Lo,et al.  Time efficient VLSI artwork analysis algorithms in GOALIE2 , 1988, DAC '88.

[15]  Ravishankar K. Iyer,et al.  Failure analysis and modeling of a VAXcluster system , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[16]  Steven D. Johnson.  Synthesis of digital designs from recursion equations , 1983 .

[17]  Hugo De Man,et al.  Transformation of Nested Loops with Modulo Indexing to Affine Recurrences , 1994, Parallel Process. Lett..

[18]  D.P. Siewiorek,et al.  A case study of C.mmp, Cm*, and C.vmp: Part I—Experiences with fault tolerance in multiprocessor systems , 1978, Proceedings of the IEEE.

[19]  Albert Seidl,et al.  CAPCAL-a 3-D capacitance solver for support of CAD systems , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  H. T. Kung,et al.  Synchronizing Large Systolic Arrays , 1982, Other Conferences.

[21]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  W. Hunt,et al.  A formal HDL and its use in the FM9001 verification , 1992, Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences.

[23]  Edward A. Lee,et al.  Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..

[24]  H. H. Chen,et al.  Wiring And Crosstalk Avoidance In Multi-chip Module Design , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[25]  Howard Trickey,et al.  Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Randal E. Bryant,et al.  Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Sang-Yong Han,et al.  Timing driven placement using complete path delays , 1990, 27th ACM/IEEE Design Automation Conference.

[28]  B. Rouzeyre,et al.  A new method for the minimization of memory area in high level synthesis , 1991, Euro ASIC '91.

[29]  Laurence A. Wolsey,et al.  Integer and Combinatorial Optimization , 1988 .

[30]  Donald E. Thomas,et al.  The system architect's workbench , 1988, DAC '88.

[31]  B. Lin,et al.  Sizing of communication buffers for communicating signal processes , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[32]  Arun K. Majumdar,et al.  Allocation of multiport memories in data path synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  M. A. Tan,et al.  Piecewise linear asymptotic waveform evaluation for transient simulation of electronic circuits , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[34]  Joos Vandewalle,et al.  Background Memory Synthesis for Algebraic Algorithms on Multi-Processor DSP Chips , 1989 .

[35]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[36]  Alberto L. Sangiovanni-Vincentelli,et al.  Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[37]  Jirí Vlach,et al.  Logic simulation with current-limited switches , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Y.-H. Choi,et al.  Configuration of boundary scan chain for optimal testing of clusters of non boundary scan devices , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[39]  Yen-Tai Lai,et al.  Layout compaction with minimized delay bound on timing critical paths , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[40]  Ugo Montanari,et al.  Networks of constraints: Fundamental properties and applications to picture processing , 1974, Inf. Sci..

[41]  Sarma B. K. Vrudhula,et al.  BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis , 1993, 30th ACM/IEEE Design Automation Conference.

[42]  Zhicheng Wang,et al.  LECSIM: a levelized event driven compiled logic simulation , 1991, DAC '90.

[43]  S. Hurst.  Detection of symmetries in combinatorial functions by spectral means , 1977 .

[44]  John P. Hayes,et al.  An Experimental MOS Fault Simulation Program CSASIM , 1984, 21st Design Automation Conference Proceedings.

[45]  Hugo De Man,et al.  Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[46]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[47]  Najmi T. Jarwala,et al.  A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[48]  David Marple.  A hierarchy preserving hierarchical compactor , 1991, DAC '90.

[49]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[50]  Robert K. Brayton,et al.  Integrating functional and temporal domains in logic design , 1991 .

[51]  Melvin A. Breuer,et al.  An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing , 1993, 30th ACM/IEEE Design Automation Conference.

[52]  E. Barnes.  An algorithm for partitioning the nodes of a graph , 1981, 1981 20th IEEE Conference on Decision and Control including the Symposium on Adaptive Processes.

[53]  Leon Stok,et al.  False loops through resource sharing , 1992, ICCAD '92.

[54]  Franc Brglez,et al.  Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults , 1992, Proceedings International Test Conference 1992.

[55]  Ralph Marlett,et al.  Selectable Length Partial Scan: A Method to Reduce Vector Length , 1991, 1991, Proceedings. International Test Conference.

[56]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[57]  Gaetano Borriello,et al.  Sizing synchronization queues: a case study in higher level synthesis , 1991, 28th ACM/IEEE Design Automation Conference.

[58]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[59]  Ravishankar K. Iyer,et al.  A Measurement-Based Model for Workload Dependence of CPU Errors , 1986, IEEE Transactions on Computers.

[60]  Somchai Prasitjutrakul,et al.  A performance-driven global router for custom VLSI chip design , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[61]  D. G. Saab,et al.  Partial reset: An inexpensive design for testability approach , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[62]  George B. Dantzig,et al.  Fourier-Motzkin Elimination and Its Dual , 1973, J. Comb. Theory, Ser. A.

[63]  Tiziano Villa,et al.  NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.

[64]  Ravishankar K. Iyer,et al.  Error Propagation in a Digital Avionic Processor: A Simulation-Based Study , 1986, RTSS.

[65]  R. J. Dakin,et al.  A tree-search algorithm for mixed integer programming problems , 1965, Comput. J..

[66]  Giovanni De Micheli,et al.  Observability don't care sets and Boolean relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[67]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[68]  E. Balas.  An Additive Algorithm for Solving Linear Programs with Zero-One Variables , 1965 .

[69]  Daniel G. Saab,et al.  CRIS: A test cultivation program for sequential VLSI circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[70]  William H. Kautz,et al.  The Necessity of Closed Circuit Loops in Minimal Combinational Circuits , 1970, IEEE Transactions on Computers.

[71]  Alberto L. Sangiovanni-Vincentelli,et al.  An incomplete scan design approach to test generation for sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[72]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[73]  Takayasu Sakurai,et al.  Simple expressions for interconnection delay, coupling and crosstalk in VLSI's , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[74]  Eduard Cerny,et al.  Self-Adjusting Networks for VLSI Simulation , 1987, IEEE Transactions on Computers.

[75]  Sharad Malik,et al.  Permutation and phase independent Boolean comparison , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[76]  Gordon D. Robinson,et al.  Interconnect testing of boards with partial boundary scan , 1990, Proceedings. International Test Conference 1990.

[77]  Steven D. Johnson,et al.  Derivation of a DRAM memory interface by sequential decomposition , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[78]  Wayne Wei-Ming Dai,et al.  Rubber band routing and dynamic data representation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[79]  George B. Dantzig,et al.  Linear programming and extensions , 1965 .

[80]  Qing Zhu,et al.  Perfect-balance planar clock routing with minimal path-length , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[81]  Pierre Gaston Paulin.  High-level synthesis of digital circuits using global scheduling and binding algorithms , 1988 .

[82]  Randal Bryant.  A Survey of Switch-Level Algorithms , 1987, IEEE Design & Test of Computers.

[83]  M.A. Lopez,et al.  A fast algorithm for VLSI net extraction , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[84]  Randal E. Bryant,et al.  A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.

[85]  Fadi J. Kurdahi,et al.  REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.

[86]  Malgorzata Marek-Sadowska,et al.  SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits , 1991, Proceedings of the European Conference on Design Automation..

[87]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[88]  Kamal Chaudhary,et al.  RITUAL: a performance driven placement algorithm , 1992 .

[89]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[90]  Alberto L. Sangiovanni-Vincentelli,et al.  Synthesis and optimization procedures for fully and easily testable sequential machines , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[91]  Mikael R. K. Patel,et al.  A design representation for high level synthesis , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[92]  David M. Lewis.  Hierarchical compiled event-driven logic simulation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[93]  G. Nemhauser,et al.  Integer Programming , 2020 .

[94]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[95]  P. Agrawal,et al.  MARS: A Multiprocessor-Based Programmable Accelerator , 1987, IEEE Design & Test of Computers.

[96]  Carl Sechen,et al.  Boolean division and factorization using binary decision diagrams , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[97]  Peter M. Maurer,et al.  Two new techniques for compiled multi-delay simulation , 1992, Proceedings IEEE Southeastcon '92.

[98]  R. Tsay.  Exact zero skew , 1991, ICCAD 1991.

[99]  David Blaauw,et al.  Hierarchical multi-level fault simulation of large systems , 1990, J. Electron. Test..

[100]  Oren Patashnik.  Optimal circuit segmentation for pseudo-exhaustive testing , 1990 .

[101]  Imtiaz Ahmad,et al.  Post-processor for data path synthesis using multiport memories , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[102]  Dhiraj K. Pradhan,et al.  High level synthesis of data driven ASICs , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[103]  Ronald A. Rohrer,et al.  ADAPTS: a digital transient simulation strategy for integrated circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[104]  Zhicheng Wang,et al.  Techniques for unit-delay compiled simulation , 1991, DAC '90.

[105]  Michael J. Flynn,et al.  An area model for on-chip memories and its application , 1991 .

[106]  John Hayes,et al.  An Introduction to Switch-Level Modeling , 1987, IEEE Design & Test of Computers.

[107]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[108]  Bo-Gwan Kim,et al.  Multilevel logic synthesis of symmetric switching functions , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[109]  A. Land,et al.  An Automatic Method for Solving Discrete Programming Problems , 1960, 50 Years of Integer Programming.

[110]  Steven D. Johnson,et al.  Toward a Basis for Protocol Specification and Process Decomposition , 1993, CHDL.

[111]  Martin D. F. Wong,et al.  Compacted channel routing with via placement restrictions , 1986, Integr..

[112]  Alberto L. Sangiovanni-Vincentelli,et al.  A New Symbolic Channel Router: YACR2 , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[113]  Alberto L. Sangiovanni-Vincentelli,et al.  Three-dimensional capacitance evaluation on a Connection Machine , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[114]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[115]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[116]  Zheng Zhu,et al.  An Algebraic Framework for Data Abstraction in Hardware Description , 1991 .

[117]  Narendra Karmarkar,et al.  A new polynomial-time algorithm for linear programming , 1984, Comb..

[118]  J. Hammersley,et al.  Monte Carlo Methods , 1965 .

[119]  Ellis Horowitz,et al.  Fundamentals of Data Structures in Pascal , 1984 .

[120]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[121]  Parimal Pal Chaudhuri,et al.  Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata , 1992, The Fifth International Conference on VLSI Design.

[122]  Hans-Joachim Wunderlich,et al.  Tools and devices supporting the pseudo-exhaustive test , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[123]  Michael Burstein,et al.  Hierarchical Channel Router , 1983, 20th Design Automation Conference Proceedings.

[124]  Tom Blank,et al.  A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.

[125]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[126]  M. Marek-Sadowska,et al.  Verifying equivalence of functions with unknown input correspondence , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[127]  Eugene C. Freuder.  A Sufficient Condition for Backtrack-Free Search , 1982, JACM.

[128]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[129]  Ibrahim N. Hajj.  An algebra for switch-level simulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[130]  Giovanni De Micheli,et al.  Technology mapping using Boolean matching and don't care sets , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[131]  Jason Cong,et al.  Provably good performance-driven global routing , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[132]  A.L. Sangiovanni-Vincentelli,et al.  A survey of third-generation simulation techniques , 1981, Proceedings of the IEEE.

[133]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[134]  Thomas Ottmann,et al.  Algorithms for Reporting and Counting Geometric Intersections , 1979, IEEE Transactions on Computers.

[135]  Takeshi Yoshimura,et al.  New placement and global routing algorithms for standard cell layouts , 1991, DAC '90.

[136]  Ben Ting,et al.  Routing Techniques for Gate Array , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[137]  Jason Cong,et al.  Performance-Driven Interconnect Design Based on Distributed RC Delay Model , 1993, 30th ACM/IEEE Design Automation Conference.

[138]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[139]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[140]  Sartaj Sahni,et al.  Time and space efficient net extractor , 1988 .

[141]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[142]  A. J. Clewett,et al.  Introduction to sequencing and scheduling , 1974 .

[143]  Arvind Srinivasan,et al.  Clock routing for high-performance ICs , 1991, DAC '90.

[144]  Robert K. Brayton,et al.  XPSim: a MOS VLSI simulator , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[145]  H. Pollak,et al.  Steiner Minimal Trees , 1968 .

[146]  A. Feller,et al.  Crosstalk and reflections in high-speed digital systems , 1965, AFIPS '65 (Fall, part I).

[147]  Rui Wang,et al.  S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function , 1992, 30th ACM/IEEE Design Automation Conference.

[148]  Russell Kao,et al.  Piecewise Linear Models for Switch-Level Simulation , 1992 .

[149]  Steven D. Johnson.  Manipulating Logical Organization with System Factorizations , 1989, Hardware Specification, Verification and Synthesis.

[150]  D. Marquardt.  An Algorithm for Least-Squares Estimation of Nonlinear Parameters , 1963 .

[151]  Alain Fournier,et al.  Triangulating Simple Polygons and Equivalent Problems , 1984, TOGS.

[152]  Jacob A. Abraham,et al.  A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[153]  Rajiv Jain,et al.  Experience with the ADAM Synthesis System , 1989, 26th ACM/IEEE Design Automation Conference.

[154]  Jason Cong,et al.  A new approach to three- or four-layer channel routing , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[155]  Melvin A. Breuer,et al.  Test Schedules for VLSI Circuits Having Built-In Test Hardware , 1986, IEEE Transactions on Computers.

[156]  Robert K. Brayton,et al.  Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[157]  Irith Pomeranz,et al.  On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation , 1994, IEEE Trans. Computers.

[158]  Han-Tzong Yuan,et al.  Properties of interconnection on silicon, sapphire, and semi-insulating gallium arsenide substrates , 1982 .

[159]  Hugo De Man,et al.  Interprocessor communication in synchronous multiprocessor digital signal processing chips , 1989, IEEE Trans. Acoust. Speech Signal Process..

[160]  Christopher J. Terman.  Simulation tools for digital LSI design , 1983 .

[161]  John P. Hayes,et al.  Pseudo-Boolean Logic Circuits , 1986, IEEE Transactions on Computers.

[162]  U. Lauther,et al.  A new global router based on a flow model and linear assignment , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[163]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[164]  Chak-Kuen Wong,et al.  An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[165]  Patrick Dewilde,et al.  SPIDER: capacitance modelling for VLSI interconnections , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[166]  Andrew B. Kahng,et al.  A direct combination of the Prim and Dijkstra constructions for improved performance-driven global routing , 1993, 1993 IEEE International Symposium on Circuits and Systems.

[167]  Jos Huisken,et al.  PHIDEO: a silicon compiler for high speed algorithms , 1991, Proceedings of the European Conference on Design Automation..

[168]  Keshab K. Parhi,et al.  Register allocation for design of data format converters , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[169]  Melvin A. Breuer,et al.  Minimal area merger of finite state machine controllers , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[170]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[171]  Sung-Mo Kang,et al.  Interconnection delay in very high-speed VLSI , 1991 .

[172]  Hanif D. Sherali,et al.  Linear Programming and Network Flows , 1977 .

[173]  Dan Adler.  Switch-level simulation using dynamic graph algorithms , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[174]  Bill Lin,et al.  Minimization of symbolic relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[175]  Ravishankar K. Iyer,et al.  FOCUS: An Experimental Environment for Fault Sensitivity Analysis , 1992, IEEE Trans. Computers.

[176]  Jan van Leeuwen,et al.  Computing the Connected Components of Simple Rectilinear Geometrical Objects in D-Space , 1984, RAIRO Theor. Informatics Appl..

[177]  Akira Onozawa.  Layout compaction with attractive and repulsive constraints , 1991, DAC '90.

[178]  Zebo Peng.  A formal methodology for automated synthesis of VLSI systems , 1987 .

[179]  Frank Vahid,et al.  Specification partitioning for system design , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[180]  Melvin A. Breuer,et al.  Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[181]  Xianlong Hong,et al.  FARM: an efficient feed-through pin assignment algorithm , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[182]  Steven D. Johnson,et al.  DDD-FM9001: Derivation of a Verified Microprocessor , 1993, CHARME.

[183]  M. W. Roberts,et al.  An algorithm for the partitioning of logic circuits , 1984 .

[184]  Massoud Pedram,et al.  Boolean matching using binary decision diagrams with applications to logic synthesis and verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[185]  Prathima Agrawal,et al.  Automatic modeling of switch-level networks using partial orders , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[186]  Alan K. Mackworth.  Consistency in Networks of Relations , 1977, Artif. Intell..

[187]  Pak K. Chan.  Comments on 'Asymptotic waveform evaluation for timing analysis' , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[188]  Kurt Spielberg,et al.  Enumerative Methods in Integer Programming , 1979 .

[189]  Ed F. Deprettere,et al.  Approximate Inversion Of Positive Definite Matrices, Specified On A Multiple Band , 1988, Optics & Photonics.

[190]  Randal E. Bryant,et al.  COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.

[191]  Jan-Ming Ho,et al.  Zero skew clock net routing , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[192]  J. Huisken,et al.  The Sprite Input Language-an intermediate format for high level synthesis , 1992, [1992] Proceedings The European Conference on Design Automation.

[193]  Eugene Shragowitz,et al.  An adaptive timing-driven layout for high speed VLSI , 1991, DAC '90.

[194]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[195]  Peter Hansen,et al.  Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[196]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[197]  Srinivas Devadas,et al.  Decomposition and factorization of sequential finite state machines , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[198]  Vishwani D. Agrawal,et al.  Initializability Consideration in Sequential Machine Synthesis , 1992, IEEE Trans. Computers.

[199]  N. C. Rumin,et al.  Magnitude classes in switch-level modeling , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[200]  Mark Horowitz,et al.  Bisim: a simulator for custom ECL circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[201]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[202]  W.F.J. Verhaegh,et al.  Relative location assignment for repetitive schedules , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[203]  Sharad Malik,et al.  Functional timing analysis using ATPG , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[204]  Christer Svensson,et al.  Fully Dynamic Switch-Level Simulation of CMOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[205]  Benoit Nadeau-Dostie,et al.  Testing of glue logic interconnects using boundary scan architecture , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[206]  J. F Cohoon,et al.  Critical net routing , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[207]  Jason Cong,et al.  High-performance clock routing based on recursive geometric matching , 1991, 28th ACM/IEEE Design Automation Conference.

[208]  W.F.J. Verhaegh,et al.  Memory synthesis for high speed DSP applications , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[209]  Linus Schrage,et al.  Linear, Integer, and Quadratic Programming with Lindo , 1984 .

[210]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[211]  Robert K. Brayton,et al.  Multi-Level Logic Simplification Using Don't Cares and Filters , 1989, 26th ACM/IEEE Design Automation Conference.

[212]  Meryem Marzouki,et al.  Model-based reasoning for electron-beam debugging of VLSI circuits , 1991, J. Electron. Test..

[213]  Alice C. Parker,et al.  CHOP: a constraint-driven system-level partitioner , 1991, 28th ACM/IEEE Design Automation Conference.