Compiled unit-delay simulation for cyclic circuits

Three techniques for handling cyclic circuits in a compiled unit-delay simulation are presented. These techniques are based on the PC-set method and the parallel technique of compiled unit-delay simulation. The first technique, called the synchronous parallel technique, is applicable only to synchronous circuits, but provides significant performance improvements over interpreted unit-delay simulation. The second and third techniques. called the convergence algorithm and the asynchronous parallel technique, are applicable to all circuits, both synchronous and asynchronous. The convergence algorithm, which is based on the PC-set method, provided significant performance increases for some circuits, but performed poorly on others. The asynchronous parallel technique performed rather poorly, and is covered only briefly.<<ETX>>