Low power CMOS circuits with clocked power

In view of changing the type of energy conversion in CMOS circuits, the authors investigate low power CMOS circuit design which adopts a gradually changing power clock. They discuss the algebraic expressions and the corresponding properties of clocked power signals. A clocked CMOS gate structure is presented and the clocked combinational circuit design is analyzed. The PSPICE simulations demonstrate the low power characteristic of clocked CMOS circuits using trapezoidal power-clock.

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