Flexible HardwareArchitecturefor AES CryptographyAlgorithm

In the numeric comm unication, much devoted efforts are dedicated to improve security and safety of numeric transactions. Hardware implementation of cryptography algorithm, as the AES, is a good solution to preserve confidentiality and accessibility to the information. In this context, this paper proposes an optimal hardware implementation of AES algorithm. Taking advantages of dynamic partially reconfigurable of FPGA. 1mplementation result of the proposed architecture shows the interest of this new approach, and confirms the contribution of the reconfigurable FPGA for robust and optimal implementation Key word: dynamic partially reconjigurable FPGA, physical implementation ofAES

[1]  Manuel Mogollon,et al.  Cryptography and Security Services: Mechanisms and Applications , 2007 .

[2]  Wei Zhang,et al.  Runtime code parallelization for on-chip multiprocessors , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[3]  Francisco Rodríguez-Henríquez,et al.  Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core , 2003, FPL.

[4]  Camel Tanougast,et al.  The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation , 2007, J. Univers. Comput. Sci..

[5]  Jürgen Becker,et al.  Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[6]  Tsutomu Sasao,et al.  An FPGA design of AES encryption circuit with 128-bit keys , 2005, ACM Great Lakes Symposium on VLSI.

[7]  Jian-Hong Chen,et al.  Reconfigurable system for high-speed and diversified AES using FPGA , 2007, Microprocess. Microsystems.

[8]  Jürgen Becker,et al.  An FPGA run-time system for dynamical on-demand reconfiguration , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[9]  Jean-Didier Legat,et al.  Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs , 2003, CHES.

[10]  Grant Martin,et al.  Surviving the SOC Revolution: A Guide to Platform-Based Design , 1999 .

[11]  Máire O'Neill,et al.  High Performance Single-Chip FPGA Rijndael Algorithm Implementations , 2001, CHES.

[12]  Jeff Mason,et al.  Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[13]  Christof Paar,et al.  Cryptography on FPGAs: State of the Art Implementations and Attacks , 2003 .

[14]  Jürgen Becker,et al.  New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[15]  Christof Paar,et al.  An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists , 2001, IEEE Trans. Very Large Scale Integr. Syst..