Embracing and Extending 20th-Century Instruction Set Architectures

A vector case study shows how new functionality can be added to extend the 80times86 and PowerPC architectures to support a full vector architecture, primarily by enhancing their multimedia extensions to provide a better model for compilers and an easier-to-understand model for programmers

[1]  David J. Lilja,et al.  So many states, so little time: verifying memory coherence in the Cray X1 , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[2]  Michael J. Flynn,et al.  Very high-speed computing systems , 1966 .

[3]  Leonid Oliker,et al.  Scientific Computations on Modern Parallel Vector Systems , 2004, Proceedings of the ACM/IEEE SC2004 Conference.

[4]  Christoforos E. Kozyrakis,et al.  Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks , 2002, MICRO.

[5]  David A. Patterson,et al.  Scalable Vector Media-processors for Embedded Systems , 2002 .

[6]  A. J. Smith,et al.  The performance impact of vector processor cashes , 1992, Proceedings of the Twenty-Fifth Hawaii International Conference on System Sciences.

[7]  Mateo Valero,et al.  Adding a vector unit to a superscalar processor , 1999, ICS '99.

[8]  Christoforos E. Kozyrakis,et al.  Scalable Vector Processors for Embedded Systems , 2003, IEEE Micro.

[9]  James E. Smith,et al.  Vector instruction set support for conditional operations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[10]  Krste Asanovic,et al.  Mondrian memory protection , 2002, ASPLOS X.

[11]  Gil Neiger,et al.  Intel virtualization technology , 2005, Computer.