A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering
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[1] Rajendran Panda,et al. Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[2] Vivek De,et al. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[3] Ankur Srivastava,et al. Active mode leakage reduction using fine-grained forward body biasing strategy , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[4] T. Chen,et al. Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[5] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[6] Andrew B. Kahng,et al. Can recursive bisection alone produce routable, placements? , 2000, Proceedings 37th Design Automation Conference.
[7] Tom W. Chen,et al. Optimization of individual well adaptive body biasing (IWABB) using a multiple objective evolutionary algorithm , 2005, Sixth international symposium on quality electronic design (isqed'05).
[8] S. Nassif,et al. Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[9] Sachin S. Sapatnekar,et al. Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.
[10] Zhi-Quan Luo,et al. Robust gate sizing by geometric programming , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[11] Jarrod A. Roy,et al. ECO-system: Embracing the Change in Placement , 2007, 2007 Asia and South Pacific Design Automation Conference.
[12] Michael Orshansky,et al. An efficient algorithm for statistical minimization of total power under timing yield constraints , 2005, Proceedings. 42nd Design Automation Conference, 2005..