NoC-based platform for embedded software design: An extension of the Hellfire Framework

This paper presents an extension of the Hellfire Framework (HFFW), providing an intuitive and powerful web interface to build, test and debug a complete Multiprocessor System-on-Chip (MPSoC). Among the new functionalities presented, it is possible to highlight: i) the architecture builder tool, used to set up all the MPSoC architecture; ii) the possibility to use a Network-on-Chip (NoC) as the communication mean, and; iii) a new simulator, providing a fast and accurate high level Instructions Set Simulator (ISS) with a miss ratio less than 5%. In order to validate the new simulator accuracy several tests were taken, first using traffic generators and then an implementation of the Secure Hash Algorithm (SHA). The achieved results are discussed throughout the paper.

[1]  Jason Cong,et al.  MC-Sim: an efficient simulation tool for MPSoC designs , 2008, ICCAD 2008.

[2]  Brent Nelson,et al.  PNoC: a flexible circuit-switched NoC for FPGA-based systems , 2006 .

[3]  Sergio Johann Filho,et al.  Hellfire: A design framework for critical embedded systems' applications , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[4]  M. Zamboni,et al.  A multiprocessor based packet-switch: performance analysis of the communication infrastructure , 2005, IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..

[5]  Luca Benini,et al.  Powering networks on chips , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

[6]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[7]  Wolfgang Rosenstiel,et al.  Network-on-Chip Architecture Exploration Framework , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[8]  Mohammed Khalid,et al.  NoC prototyping on FPGAs: A case study using an image processing benchmark , 2009, 2009 IEEE International Conference on Electro/Information Technology.

[9]  Rainer Leupers,et al.  A high-level virtual platform for early MPSoC software development , 2009, CODES+ISSS '09.

[10]  Christof Paar,et al.  Understanding Cryptography: A Textbook for Students and Practitioners , 2009 .

[11]  Luca Benini,et al.  MPARM: Exploring the Multi-Processor SoC Design Space with SystemC , 2005, J. VLSI Signal Process..

[12]  Ahmed Amine Jerraya,et al.  Automatic generation of fast timed simulation models for operating systems in SoC design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[13]  César A. M. Marcon,et al.  High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping , 2008, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping.

[14]  Gerry Kane,et al.  MIPS RISC Architecture , 1987 .

[15]  Jean Paul Calvez,et al.  A generic RTOS model for real-time systems simulation with systemC , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.