Extending Synchronization from Super-Threshold to Sub-threshold Region

Ultra low voltage operation promises to reduce power dissipation for wireless sensor network applications. Such ultra low voltage systems are likely to have many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold. Synchronizers are needed to interface among these domains. However, VDD scaling rapidly degrades synchronizers performance making them unsuitable for ultra low voltage operation. Here, we analyze the performance of two existing synchronizers at ultra low voltages and propose to apply forward body bias to the synchronizer latch to extend its operation to sub-threshold region with an acceptable performance and to make them process variation resilient. We show that by using full-VDD bias, synchronizer performance can be improved by more than 80%. We also study the impact of process variation on the synchronization time and found that with full-VDD bias 9X improvement in the synchronization time can be achieved for the worst case corner. Finally, we propose a simple implementation scheme of body-biased synchronizer which improves the synchronizer performance significantly at ultra low voltages with nearly zero overhead and can be configured to work for a wide range of VDDs from sub-threshold region to nominal VDD.

[1]  Massoud Pedram,et al.  Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..

[2]  Margaret Martonosi,et al.  An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[3]  Massoud Pedram,et al.  Power Aware Design Methodologies , 2002 .

[4]  Jun Zhou,et al.  Adapting Synchronizers to the Effects of on Chip Variability , 2008, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.

[5]  Harry Veendrick.  Nanometer CMOS ICs: From Basics to ASICs , 2008 .

[6]  Jun Zhou,et al.  On-Chip Measurement of Deep Metastability in Synchronizers , 2008, IEEE Journal of Solid-State Circuits.

[7]  Suwen Yang,et al.  Computing Synchronizer Failure Probabilities , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[8]  Mladen Berekovic,et al.  Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring , 2007, SAMOS.

[9]  C. Dike,et al.  Miller and noise effects in a synchronizing flip-flop , 1999 .

[10]  David J. Kinniment,et al.  Synchronization circuit performance , 2002 .

[11]  A.P. Chandrakasan,et al.  A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter , 2008, IEEE Journal of Solid-State Circuits.

[12]  Yajun Ha,et al.  An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[13]  Bo Zhai,et al.  A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[14]  Stuart N. Wooters,et al.  A 2.6-µW sub-threshold mixed-signal ECG SoC , 2009, 2009 Symposium on VLSI Circuits.

[15]  Hendrikus J. M. Veendrick,et al.  The behaviour of flip-flops used as synchronizers and prediction of their failure rate , 1980 .

[16]  Gordon Russell,et al.  Measuring deep metastability , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[17]  Naveen Verma,et al.  A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[18]  Harry J.M. Veendrick,et al.  Nanometer CMOS ICs , 2008 .

[19]  Jun Zhou,et al.  A robust synchronizer , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[20]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[21]  David Z. Pan,et al.  A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[22]  C. Dike,et al.  A fast resolving BiNMOS synchronizer for parallel processor interconnect , 1995 .