An analysis of full adder cells for low-power data oriented adders design

This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values than traditional model, based on switching activity only. Obtained results allow analyzing what structure of full adder should be used for specific data summation. So, such model and analyses can lead to developing of data oriented low power design methods. Based on energetic parameters assessed for 1-bit full adders, multi-bit adders were considered. Theirs power consumption versus summed data was analyzed.

[1]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[2]  A. Kos,et al.  Calculation methods of new circuit activity measure for low power modeling , 2008, 2008 International Conference on Signals and Electronic Systems.

[3]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[4]  Ireneusz Brzozowski,et al.  Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation , 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

[5]  Jim D. Garside.  A CMOS VLSI Implementation of an Asynchronous ALU , 1993, Asynchronous Design Methodologies.

[6]  Lizy Kurian John,et al.  A novel low power energy recovery full adder cell , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[7]  Omid Kavehei,et al.  Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell , 2008, J. Comput..